1. Field of the Invention
The present invention relates generally to the field of computer systems and, in particular, to a method and apparatus for providing a segmentation and reassembly (SAR) engine which is independent of interface protocol and which can be interfaced to an Asynchronous Transfer Mode (ATM) Cell Interface operating at a different data rate.
2. Description of the Related Art
ATM technology is emerging as the preferred technology for sending information at very high speeds between a transmission point and one or more receiving points. An ATM system facilitates the transmission of data over such a network by defining a set of "data connections" in which each connection represents a virtual circuit having a particular source and destination and an associated data transmission rate.
One particular implementation of an ATM system employs a Cell Interface block configured to implement a Universal Test and Operational Physical Interface (UTOPIA) protocol. The Cell Interface block receives cells from the ATM Layer Core for transfer to the ATM Cell Interface (I.E., UTOPIA). The Cell Interface block also receives cells from the ATM Cell Interface for forwarding to the ATM Layer Core for reassembly into packets for eventual transfer to the host device or local area network (LAN).
Typically, data is transferred over the ATM network using short bursts of 53-byte cells. Each cell consists of 5-header bytes and 48-data bytes. The data stream over the ATM network sent to a particular host device may consist of interleaved cells belonging to several virtual circuits. A receiver at the host device assembles these cells separately depending on which virtual circuit the incoming cell belongs to. Conversely, a transmitter segments the data to be sent across one or more virtual circuits into cells and transmits them according to a predetermined order in a single stream. Thus, cells destined to a particular host device are sent along to a particular virtual circuit.
One technique of segmentation and reassembly includes cellification over the Input/Output (I/O) bus through which data in 48-byte cells are provided from a SAR circuit to a host device or vice versa. This technique however, results in a bottleneck at the I/O bus and is thus inefficient. A second technique involves segmentation and reassembly of the data cells on the SAR circuit between the host and Cell Interface block. Although this technique results in greater efficiency in data transmission over the prior technique, there is bandwidth and data mismatch between the buffer memory, where data to be transmitted and data that is received is stored, and the Cell Interface block. This is because the buffer provides data through a 32-bit data path, while the Cell Interface block supports an 8-bit stream at 20 MHz for 155 Mbps or a 16-bit stream at 40 MHz for a 622 Mbps data stream.
In addition, current standard specifies rates over the ATM network ranging from 25 Mbits to 2.4 Gigabits/second. To conform to the UTOPIA specification, the Cell Interface block has to support an 8-bit stream at 20-25 MHz for 155 Mbps or a 16-bit stream at 40-50 MHz for a 622 Mbps data stream. One problem, in providing such a Cell Interface block, is accounting for the requirements of the two data rates. This is particularly problematic because of possible phase delays of generally unknown duration, occurring between the clock signals operating internally within the ATM Layer Core on the SAR circuit and the clock driving the ATM Cell Interface. In other systems, similar phase or timing delays are accounted for by iteratively tuning the relative phases of the separate systems, perhaps by inserting various delay lines. The need to iteratively tune a system, however, adds to the overall cost of developing the system.
Accordingly, there is a need in the technology to provide a system for interfacing with a Cell Interface block which is not only capable of operating efficiently at different transmission rates, but which also insulates the details of such operation from the ATM Layer Core within the SAR engine.